-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "12/19/2021 16:46:09"

-- 
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	seq_detector IS
    PORT (
	clk : IN std_logic;
	din : IN std_logic;
	odd_t : OUT std_logic;
	y : OUT std_logic
	);
END seq_detector;

-- Design Ports Information
-- odd_t	=>  Location: PIN_N9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- y	=>  Location: PIN_L7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- din	=>  Location: PIN_L5,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF seq_detector IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_din : std_logic;
SIGNAL ww_odd_t : std_logic;
SIGNAL ww_y : std_logic;
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \ps.seven~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \odd_t~output_o\ : std_logic;
SIGNAL \y~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \din~input_o\ : std_logic;
SIGNAL \ns.eight~0_combout\ : std_logic;
SIGNAL \ps.eight~q\ : std_logic;
SIGNAL \Selector0~0_combout\ : std_logic;
SIGNAL \ps.idle~q\ : std_logic;
SIGNAL \ns~2_combout\ : std_logic;
SIGNAL \ps.one~q\ : std_logic;
SIGNAL \ns.two~0_combout\ : std_logic;
SIGNAL \ps.two~feeder_combout\ : std_logic;
SIGNAL \ps.two~q\ : std_logic;
SIGNAL \ns.three~0_combout\ : std_logic;
SIGNAL \ps.three~feeder_combout\ : std_logic;
SIGNAL \ps.three~q\ : std_logic;
SIGNAL \ns.four~0_combout\ : std_logic;
SIGNAL \ps.four~feeder_combout\ : std_logic;
SIGNAL \ps.four~q\ : std_logic;
SIGNAL \ns.five~0_combout\ : std_logic;
SIGNAL \ps.five~feeder_combout\ : std_logic;
SIGNAL \ps.five~q\ : std_logic;
SIGNAL \ns.six~0_combout\ : std_logic;
SIGNAL \ps.six~feeder_combout\ : std_logic;
SIGNAL \ps.six~q\ : std_logic;
SIGNAL \ns.seven~0_combout\ : std_logic;
SIGNAL \ps.seven~feeder_combout\ : std_logic;
SIGNAL \ps.seven~q\ : std_logic;
SIGNAL \ps.seven~clkctrl_outclk\ : std_logic;
SIGNAL \Selector1~0_combout\ : std_logic;
SIGNAL \temp~0_combout\ : std_logic;
SIGNAL \temp~1_combout\ : std_logic;
SIGNAL \Selector3~0_combout\ : std_logic;
SIGNAL \odd_t$latch~combout\ : std_logic;
SIGNAL \y$latch~combout\ : std_logic;
SIGNAL test : std_logic_vector(7 DOWNTO 0);
SIGNAL \ALT_INV_din~input_o\ : std_logic;

BEGIN

ww_clk <= clk;
ww_din <= din;
odd_t <= ww_odd_t;
y <= ww_y;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\ps.seven~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \ps.seven~q\);
\ALT_INV_din~input_o\ <= NOT \din~input_o\;

-- Location: IOOBUF_X20_Y0_N2
\odd_t~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \odd_t$latch~combout\,
	devoe => ww_devoe,
	o => \odd_t~output_o\);

-- Location: IOOBUF_X14_Y0_N2
\y~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \y$latch~combout\,
	devoe => ww_devoe,
	o => \y~output_o\);

-- Location: IOIBUF_X16_Y0_N15
\clk~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G17
\clk~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: IOIBUF_X14_Y0_N8
\din~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_din,
	o => \din~input_o\);

-- Location: LCCOMB_X15_Y1_N14
\ns.eight~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.eight~0_combout\ = (\ps.seven~q\ & \din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \ps.seven~q\,
	datad => \din~input_o\,
	combout => \ns.eight~0_combout\);

-- Location: FF_X15_Y1_N15
\ps.eight\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~input_o\,
	d => \ns.eight~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.eight~q\);

-- Location: LCCOMB_X15_Y1_N28
\Selector0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \Selector0~0_combout\ = \din~input_o\ $ (((\ps.four~q\) # (\ps.two~q\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111101011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.four~q\,
	datac => \din~input_o\,
	datad => \ps.two~q\,
	combout => \Selector0~0_combout\);

-- Location: FF_X15_Y1_N29
\ps.idle\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~input_o\,
	d => \Selector0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.idle~q\);

-- Location: LCCOMB_X15_Y1_N2
\ns~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns~2_combout\ = (\ps.eight~q\) # (!\ps.idle~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \ps.eight~q\,
	datad => \ps.idle~q\,
	combout => \ns~2_combout\);

-- Location: FF_X15_Y1_N27
\ps.one\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	asdata => \ns~2_combout\,
	sclr => \ALT_INV_din~input_o\,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.one~q\);

-- Location: LCCOMB_X14_Y1_N18
\ns.two~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.two~0_combout\ = (\din~input_o\ & \ps.one~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \din~input_o\,
	datac => \ps.one~q\,
	combout => \ns.two~0_combout\);

-- Location: LCCOMB_X14_Y1_N22
\ps.two~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.two~feeder_combout\ = \ns.two~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \ns.two~0_combout\,
	combout => \ps.two~feeder_combout\);

-- Location: FF_X14_Y1_N23
\ps.two\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.two~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.two~q\);

-- Location: LCCOMB_X14_Y1_N24
\ns.three~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.three~0_combout\ = (\ps.two~q\ & !\din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010001000100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.two~q\,
	datab => \din~input_o\,
	combout => \ns.three~0_combout\);

-- Location: LCCOMB_X14_Y1_N4
\ps.three~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.three~feeder_combout\ = \ns.three~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \ns.three~0_combout\,
	combout => \ps.three~feeder_combout\);

-- Location: FF_X14_Y1_N5
\ps.three\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.three~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.three~q\);

-- Location: LCCOMB_X14_Y1_N26
\ns.four~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.four~0_combout\ = (\ps.three~q\ & \din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.three~q\,
	datac => \din~input_o\,
	combout => \ns.four~0_combout\);

-- Location: LCCOMB_X14_Y1_N8
\ps.four~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.four~feeder_combout\ = \ns.four~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \ns.four~0_combout\,
	combout => \ps.four~feeder_combout\);

-- Location: FF_X14_Y1_N9
\ps.four\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.four~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.four~q\);

-- Location: LCCOMB_X14_Y1_N16
\ns.five~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.five~0_combout\ = (\ps.four~q\ & !\din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.four~q\,
	datac => \din~input_o\,
	combout => \ns.five~0_combout\);

-- Location: LCCOMB_X15_Y1_N8
\ps.five~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.five~feeder_combout\ = \ns.five~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \ns.five~0_combout\,
	combout => \ps.five~feeder_combout\);

-- Location: FF_X15_Y1_N9
\ps.five\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.five~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.five~q\);

-- Location: LCCOMB_X14_Y1_N12
\ns.six~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.six~0_combout\ = (\ps.five~q\ & \din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.five~q\,
	datab => \din~input_o\,
	combout => \ns.six~0_combout\);

-- Location: LCCOMB_X14_Y1_N14
\ps.six~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.six~feeder_combout\ = \ns.six~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ns.six~0_combout\,
	combout => \ps.six~feeder_combout\);

-- Location: FF_X14_Y1_N15
\ps.six\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.six~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.six~q\);

-- Location: LCCOMB_X15_Y1_N26
\ns.seven~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ns.seven~0_combout\ = (\ps.six~q\ & \din~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \ps.six~q\,
	datab => \din~input_o\,
	combout => \ns.seven~0_combout\);

-- Location: LCCOMB_X15_Y1_N6
\ps.seven~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \ps.seven~feeder_combout\ = \ns.seven~0_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \ns.seven~0_combout\,
	combout => \ps.seven~feeder_combout\);

-- Location: FF_X15_Y1_N7
\ps.seven\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \ps.seven~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \ps.seven~q\);

-- Location: CLKCTRL_G15
\ps.seven~clkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \ps.seven~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \ps.seven~clkctrl_outclk\);

-- Location: LCCOMB_X14_Y1_N30
\test[2]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(2) = (\ps.two~q\ & ((\din~input_o\))) # (!\ps.two~q\ & (test(2)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => test(2),
	datac => \ps.two~q\,
	datad => \din~input_o\,
	combout => test(2));

-- Location: LCCOMB_X14_Y1_N28
\test[3]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(3) = (\ps.three~q\ & ((\din~input_o\))) # (!\ps.three~q\ & (test(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => test(3),
	datac => \ps.three~q\,
	datad => \din~input_o\,
	combout => test(3));

-- Location: LCCOMB_X15_Y1_N20
\test[1]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(1) = (\ps.one~q\ & ((\din~input_o\))) # (!\ps.one~q\ & (test(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => test(1),
	datac => \ps.one~q\,
	datad => \din~input_o\,
	combout => test(1));

-- Location: LCCOMB_X15_Y1_N22
\Selector1~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \Selector1~0_combout\ = ((\ps.eight~q\ & \din~input_o\)) # (!\ps.idle~q\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000011111111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \ps.eight~q\,
	datac => \din~input_o\,
	datad => \ps.idle~q\,
	combout => \Selector1~0_combout\);

-- Location: LCCOMB_X15_Y1_N24
\test[0]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(0) = (\Selector1~0_combout\ & ((\din~input_o\))) # (!\Selector1~0_combout\ & (test(0)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => test(0),
	datac => \Selector1~0_combout\,
	datad => \din~input_o\,
	combout => test(0));

-- Location: LCCOMB_X15_Y1_N4
\temp~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \temp~0_combout\ = test(2) $ (test(3) $ (test(1) $ (test(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => test(2),
	datab => test(3),
	datac => test(1),
	datad => test(0),
	combout => \temp~0_combout\);

-- Location: LCCOMB_X14_Y1_N20
\test[6]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(6) = (\ps.six~q\ & ((\din~input_o\))) # (!\ps.six~q\ & (test(6)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => test(6),
	datac => \ps.six~q\,
	datad => \din~input_o\,
	combout => test(6));

-- Location: LCCOMB_X14_Y1_N10
\test[4]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(4) = (\ps.four~q\ & ((\din~input_o\))) # (!\ps.four~q\ & (test(4)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => test(4),
	datac => \ps.four~q\,
	datad => \din~input_o\,
	combout => test(4));

-- Location: LCCOMB_X15_Y1_N16
\test[5]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(5) = (\ps.five~q\ & ((\din~input_o\))) # (!\ps.five~q\ & (test(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => test(5),
	datac => \ps.five~q\,
	datad => \din~input_o\,
	combout => test(5));

-- Location: LCCOMB_X15_Y1_N0
\test[7]\ : cycloneiv_lcell_comb
-- Equation(s):
-- test(7) = (GLOBAL(\ps.seven~clkctrl_outclk\) & ((\din~input_o\))) # (!GLOBAL(\ps.seven~clkctrl_outclk\) & (test(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => test(7),
	datac => \din~input_o\,
	datad => \ps.seven~clkctrl_outclk\,
	combout => test(7));

-- Location: LCCOMB_X15_Y1_N10
\temp~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \temp~1_combout\ = test(6) $ (test(4) $ (test(5) $ (test(7))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0110100110010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => test(6),
	datab => test(4),
	datac => test(5),
	datad => test(7),
	combout => \temp~1_combout\);

-- Location: LCCOMB_X15_Y1_N18
\Selector3~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \Selector3~0_combout\ = (\ps.eight~q\ & (\temp~0_combout\ $ (!\temp~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \temp~0_combout\,
	datac => \ps.eight~q\,
	datad => \temp~1_combout\,
	combout => \Selector3~0_combout\);

-- Location: LCCOMB_X15_Y1_N12
\odd_t$latch\ : cycloneiv_lcell_comb
-- Equation(s):
-- \odd_t$latch~combout\ = (GLOBAL(\ps.seven~clkctrl_outclk\) & (\odd_t$latch~combout\)) # (!GLOBAL(\ps.seven~clkctrl_outclk\) & ((\Selector3~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \odd_t$latch~combout\,
	datac => \ps.seven~clkctrl_outclk\,
	datad => \Selector3~0_combout\,
	combout => \odd_t$latch~combout\);

-- Location: LCCOMB_X15_Y1_N30
\y$latch\ : cycloneiv_lcell_comb
-- Equation(s):
-- \y$latch~combout\ = (GLOBAL(\ps.seven~clkctrl_outclk\) & ((\y$latch~combout\))) # (!GLOBAL(\ps.seven~clkctrl_outclk\) & (\ps.eight~q\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \ps.eight~q\,
	datac => \y$latch~combout\,
	datad => \ps.seven~clkctrl_outclk\,
	combout => \y$latch~combout\);

ww_odd_t <= \odd_t~output_o\;

ww_y <= \y~output_o\;
END structure;


